Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters∗
نویسندگان
چکیده
Nanometer CMOS VLSI circuits are highly sensitive to soft errors, also known as single-event upsets (SEU) that induce current pulses at random times and at random locations in a digital circuit. Environmental causes of SEU include cosmic radiation and high-energy particles. Our neutron induced soft error rate (SER) estimation method propagates single event transient (SET) pulses through the affected logic circuit. A pulse is modeled by two parameters, a probability of occurrence and a probability density function of the pulse width. We consider the entire neutron linear energy transfer (LET) spectra of the terrestrial background in our analysis. Failures in time (FIT) rates are calculated for ISCAS85 benchmark circuits. In comparison to the reported SER analysis work, our method considered many more factors like the sensitive region of a device, electrical masking and circuit technology that influence the SER. A comparison with measured SER for SRAMs shows better relevancy of our work over other published work. Our CPU times are reasonable; benchmark circuit C1908 with 880 gates requires only 1.14 seconds. We conclude that soft error estimation is highly sensitive to factors like sensitive regions, process variation and circuit characterization. Field test or accelerated test data on logic devices would be needed to further validate the accuracy of the analysis.
منابع مشابه
A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic
Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increasingly important in combinational logic circuits. Combinational logic is resilient to soft errors due to three masking phenomena: (1) Logical Masking, (2) Electrical Masking, and (3) Latching-window Masking. This paper concentrates on logical masking, and proposes a probabilistic model which calcu...
متن کاملA Stimulus-free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of Single-EventUpset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstr...
متن کاملSoft Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by sin...
متن کاملImproving the Soft-error Tolerability of a Soft-core Processor on an FPGA using Triple Modular Redundancy and Partial Reconfiguration
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which can be induced by radiation effects. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. In this work, we propose techniques for SEU mitigation and recovery of a soft-core processor using triple modular redundancy (TMR) and partial reconf...
متن کاملA Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) o...
متن کامل